The present invention relates in general to semiconductor technology, and more particularly to power semiconductor devices having high breakdown voltage, low on-resistance, and small switching loss.
A power semiconductor device such as a power metal oxide semiconductor field effect transistor (MOSFET) is required to have high breakdown voltage, low on-resistance, and small switching loss. FIG. 1 is a layout view of a conventional power MOSFET, and FIG. 2 is a sectional view taken along line A-A′ in FIG. 1. In FIGS. 1 and 2, like references are used to refer to like regions, layers, or portions throughout. In FIG. 1, a plurality of hexagonal unit cells 100 are spaced-apart from one another by a predetermined distance d so as to obtain an optimum breakdown voltage and on-resistance. The predetermined distance d between the hexagonal unit cells 100 is the same as a width d of a gate electrode 118. Each of hexagonal unit cells 100 has a source region 108 of n+-type conductivity which is overlapped by gate electrode 118 and source electrode 120.
In FIG. 2, an n−-type drift region 104 extends over an n+-type drain region 102. Body regions 106 of p−-type conductivity are formed in an upper portion of n−-type drift region 104. Source regions 108 of n+-type conductivity are formed in an upper portion of p−-type body regions 106. Highly-doped regions 110 of p+-type conductivity are formed in p−-type body regions 106, and extend from a surface area of body regions 106 between source regions 108 to a depth terminating in drift region 104. Highly-doped region 112 of n+-type conductivity is formed in an upper potion of n−-type drift region 104 between p−-type body regions 106. Highly doped (n+) region 112 is deeper than source regions 108 but shallower than highly-doped (p+) regions 110. Gate insulating layers 116 extend over channel regions 114 and highly-doped (n+) regions 112, and overlap source regions 108. Gate electrode 118 extends over gate insulating layers 116. Source electrode 120 contacts source regions 108 and highly-doped (p+) regions 110. A drain electrode 122 contacts n+-type drain region 102.
In the hexagonal unit cell structure of FIGS. 1 and 2 reducing distance d between adjacent hexagonal unit cells 100 increases the channel density per unit area which reduces the device on-resistance. A further benefit of reducing distance d is that it leads to an improvement in the switching speed of the device. This is because reducing the distance d by reducing the spacing between adjacent body regions 106 results in a reduction in the total overlap area between gate electrodes 118 and highly doped (n+) regions 112. This in turn results in a reduction in the gate to drain capacitance (Cgd) and thus an improvement in the device switching speed. Furthermore, a lower Cgd results in lower switching power loss.
Reducing the distance d however has the draw back of increasing the on-resistance of the device. This is because reducing the spacing between adjacent body regions 106 increases the resistance in the JFET region (i.e., the region between base regions 106). Moreover, because of the relatively shallow depth of highly doped (n+) regions 112, reducing the spacing between body regions 106 reduces the effectiveness of highly doped (n+) regions 112 in minimizing the resistance in the JFET region.
In addition, because of the hexagonal shape of units cells 100, the depletion region formed across the reverse-biased junction between drift region 104 and body regions 106 has a spherical shape. This results in lower breakdown voltage. To improve the breakdown voltage, it is necessary to increase the resistivity and/or a thickness of drift region 104. However this would lead a higher on-resistance
Thus, a power device structure and method of forming the same which has a low on-resistance, high breakdown voltage, fast switching speed, and low switching loss is desirable.